- Release Year: 2005
- Platforms: Windows
- Publisher: Jake Birkett Computer Solutions Ltd.
- Developer: Jake Birkett Computer Solutions Ltd.
- Genre: Action
- Perspective: Top-down
- Game Mode: Single-player
- Gameplay: Arcade, Shooter
- Setting: Futuristic, Sci-fi

Description
Jewel of Orion is a vertical-scrolling space shooter released in 2005, where players navigate a spacecraft through levels, destroying moons and aliens to score points. The game features simple controls, progressive firepower upgrades, and a challenge to survive ten levels while managing three lives.
Based on the provided PDF content, this appears to be a Digital Design textbook titled “Digital Design: A Systems Approach”. Here’s a structured summary of its content:
Key Chapters & Topics
-
Introduction
- Digital system examples (computers, smartphones, medical devices).
- Design methodologies: Top-down vs. bottom-up approaches.
- Metrics: Area, power, performance, and testability.
-
Basics of Digital Circuits
- Digital Abstraction: Translating physical signals into binary values (0/1).
- CMOS Technology:
- NMOS/PMOS transistors, logic gates (NOT, NAND, NOR).
- Voltage levels, noise margins, and propagation delays.
- Basic Gates: Properties of combinational gates (e.g., fan-in, fan-out).
-
Combinational Logic Design
- Boolean Algebra: Laws, theorems, and simplification techniques.
- Karnaugh Maps (K-maps): Minimization of Boolean expressions.
- Combinational Blocks: Multiplexers, decoders, adders, and comparators.
- Timing Hazards: Glitch analysis and solutions.
-
Sequential Logic Design
- Latches & Flip-Flops: SR, D, JK, and T types.
- Finite State Machines (FSMs):
- Moore and Mealy models.
- State encoding and optimization.
- Asynchronous Circuits: Hazards and synchronization.
-
Memory and Programmable Logic
- Memory Types: ROM, RAM (SRAM/DRAM), and non-volatile memory.
- Programmable Logic:
- PALs, PLAs, CPLDs, and FPGAs.
- FPGA architecture and design flow.
- Memory Testing: Fault models and BIST (Built-in Self-Test).
-
Design for Testability (DFT)
- Scan Design: Shift registers for sequential circuit testing.
- Boundary Scan: JTAG standards.
- Test Compression: ATPG (Automatic Test Pattern Generation).
-
Appendices & References
- Appendix A: Symbol reference.
- Appendix B: Glossary.
- Appendix C: Verilog/VHDL quick reference.
- References: Key textbooks and papers (e.g., by Harris, Roth, etc.).
Notable Features
- Practical Focus: Emphasis on real-world design trade-offs (area, power, speed).
- Visual Aids: Includes CMOS schematics, timing diagrams, and state machine diagrams.
- Design Tools: Mentions FPGA tools (Xilinx/Altera) and HDLs (Verilog/VHDL).
- Problem Sets: Each chapter includes exercises for hands-on learning.
Audience
- Undergraduate students in Electrical/Computer Engineering.
- Engineers seeking foundational knowledge in digital circuit design.
This textbook provides a comprehensive introduction to digital design, balancing theory with practical implementation strategies. For specific questions (e.g., CMOS timing, FSM design), ask for details!